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1 ZIF600 the ZIF600 synthesiser is for channel selection in 4fsk pagers. a reference frequency is generated by an on-chip crystal oscillator with an afc external trimming varacator controlled by a dac. the ZIF600 digital demodulator uses dsp techniques to optimise the data extraction in the presence of noise and also generates an afc output to adjust the crystal frequency. separate power controls allow the system current consumption to be minimised. all functions are controlled by a serial bus with a simple programming format and with four control pins which are used to control the power up and power down functions of the blocks to allow sequenced wake up and optimised power consumption. features n low voltage operation, 2.7 to 3.3v n on-chip reference oscillator n channel select synthesiser n direct vco input at up to 330mhz n 6400 baud digital 4fsk demodulator n serial control bus n very low power consumption n small qsop24 package fig.1 pin connections - top view qp24 applications n pagers - including small form factor designs such as credit card pagers, watch pagers and pcmcia applications n low data rate receivers - security/remote control absolute maximum ratings to be defined. fig.2 ZIF600 block diagram ZIF600 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 rxq rxi srf data0 data1 vssd vddd vref rbias pdout pllc dacout dsc2 dsc1 data le clock vssa vcofin vdda refoscb tss refosc vssi rxi rxq phase detector control logic & power management dsc2 data1 refosc refosb vcofin data clock vdda vddd tss vssa pllc srf vssi biases vref rbias data slicer afc (dac) digital demodulator reference divider m and a dividers le dsc1 dacout pdout data0 two modulus prescaler vssd limi limq demod. clock ZIF600 pager synthesiser and 4fsk demodulator ds4771 - 1.2 october 1997
2 ZIF600 target electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated): vddd, vdda = 2.7 to 3.3v, vdd1 = 0.95v to 1.6v (connected to refoscb via ext. resistor) and t amb = ?20 to + 70 c characteristic min. typ. max. units conditions supply current at vddd,vdda = 3v - 1 - ma synthesiser locked and demodulator active. vdd1 supply current at vdd1 = 1.4v - 350 - m a connected to refoscb via external resistor. vref bias voltage input range 1.15 1.25 1.31 v logic input high, pins data, clock, vdd - 0.3 - vdd + 0.3 v le, dsc1, dsc2, pllc, srf, rxi, rxq logic input high, pins data, clock, vss - 0.3 - vss + 0.3 v le, dsc1, dsc2, pllc, srf, rxi, rxq input capacitance (signal pins) - - 10 pf pin voltage: vss to vdd input leakage (signal pins) - - 1 m a pin voltage: vss to vdd control bus clock frequency 0 - 10 mhz synthesiser charge pump output - 50 - na pin voltage: leakage, pin pdout vss to vdd synthesiser charge pump output 160 200 240 m a pin vdd/2 current, pin pdout charge pump output compliance vss + 0.4 - vdd ? 0.4 v current within 10% of its range, pin pdout value at vdd/2 main synthesiser input frequency on 50 - 330 mhz vcofin vcofin input level 300 - 1000 mv pk - pk reference frequency crystal - 12.8 - mhz pins refosc and 14.4 refoscb logic output high, pins data0, vdd ? 0.3 - vdd v output current, ioh = data1 100 m a logic output low, pins data0, vss - vss ? 0.3 v output current, iol = data1 100 m a. trim dac output voltage, pin dacout 0 - 2.375 v not tested output current 100na vref = 1.25v rxi, rxq pull-up current 1.5 - - m a vdd ? 0.3v rxi, rxq pull-up current - - 40 m a vss + 0.3v input leakage (signal) pins with - - 3 m a pin voltage: vss to vdd pull-downs pins include srf, pllc dsc1, dsc2
3 ZIF600 functional description the ZIF600 synthesiser is used to select the channel in 4fsk paging receivers and uses on-chip constant current charge pumps to drive an external passive loop filter. common low cost reference crystals are used, at frequencies of 12.8 or 14.4mhz, and are divided to give the required 12.5, 20 or 25khz channel spacings. the reference crystal oscillator uses external trimming to meet system requirements and is controlled by a dac set by the digital demodulator. the digital demodulator takes the limited i and q signals from the radio receiver and converts the 4-level fsk into 2 bit data output on pins data0 and data1. an afc output from this demodulator is also included. functions are controlled by a serial bus with a simple programming format and with four control pins to allow optimum power up sequences which help minimise the system current consumption. description of functions pin no. pin name pin type description 1 rxq in receiver "quadrature" output 2 rxi in receiver "in phase" output 3 srf in symbol rate filter 4 data0 out data output to decoder 5 data1 out data output to decoder 6 vssd g digital ground 7 vddd p 2.7 to 3.3v digital power supply 8 vref in 1.25 volt reference from zif100 9 rbias in bias setting resistor 120k w to vssa max. parasitic capacitance = 5pf 10 pdout out charge pump output from synthesiser 11 pllc in synthesiser power down 12 dacout out trim dac for crystal 13 vss1 g ground (substrate) 14 refosc i/o reference oscillator 15 tss in test scan select, normally logic 0 16 refoscb i/o reference oscillator. external resistor to vdd1 17 vdda p 2.7 to 3.3v analog power supply 18 vcofin in vco frequency input to synthesiser 19 vssa g analog ground 20 clock in control bus clock 21 le in control bus latch enable 22 data in control bus data 23 dsc1 in with dsc2 controls the operating mode of the demodulator 24 dsc2 in with dsc1 controls the operating mode of the demodulator table 1. list of pins reference dividers the reference frequency generated by the oscillator on pins refosc and refoscb is divided to give the comparison frequency clock. see fig. 3. ratio selection is five control bits rd1 (where low gives ? 8 mode), rd2 (where low gives ? 4 mode) and rd3 (where low gives ? 2 mode) which can be set to give the 8 options needed to get 10khz, 12.5khz, 20khz or 25khz from either a 12.8 or 14.4mhz crystal, as in table 2. the additional control bits rd4 and rd5 allow the option of further division to allow for an off chip frequency multiplier. if both rd4 and rd5 are set low then this division stage is bypassed. other settings for rd4 and rd5 offer division by 2, 3 or 4. table 3 shows the additional division options available from rd4 and rd5. power down options are available for both the synthesiser and demodulator, however the crystal oscillator and the reference divider must be kept running to give a timing signal to the demodulator whilst the demodulator is on. table 2 reference divider ratios crystal comp. total rd1 rd2 rd3 mhz freq. khz division 12.8 25 512 0 0 0 14.4 25 576 1 0 0 12.8 20 640 0 1 0 14.4 20 720 1 1 0 12.8 12.5 1024 0 0 1 14.4 12.5 1152 1 0 1 12.8 10 1280 0 1 1 14.4 10 1440 1 1 1 table 3 additional divider ratios additional division rd4 rd5 bypass 0 0 201 310 411
4 ZIF600 synthesiser the synthesiser divides the vcofin frequency by the 16- bit number fch programmed from the serial bus and then the phase detector compares the result with the comparison frequency signal to generate correction pulses. the division ratio range is 4,032 to 65,535. an embedded two modulus prescaler is used to minimise power consumption but its programming is arranged to be transparent to the user. by using a digital phase and frequency detector the loop will pull in over an unlimited range and then by using a reset signal fed back from the output current drivers any delays in the output path do not give a dead band in the phase response. the charge pump currents are set by internal biasing. the current level fixed by the circuit has been selected to give minimum loop disturbance from external interference, while also not taking excessive current from the supply line. it is expected that adequate high frequency decoupling will be provided on the power supplies to eliminate any significant noise. powering up the synthesiser requires that vref, ibias and pllc have been turned on for an adequate time before the synthesiser is required to be functioning. as the demodulator takes its clock from the synthesiser reference divider, the synthesiser reference oscillator and divider circuits must be on and have settled before the demodulator is turned on. setting the "dmo" bit in the control bus allows the main parts of the synthesiser to be kept in a low power mode with only the reference oscillator and reference divider operating, when pllc is high. this effectively allows the demodulator to be used standalone with its required clock being provided by the reference oscillator/divider. fig.4 basic block diagram of synthesiser "dmo" bit pllc synthesiser mode 0 0 synthesiser off 1 0 synthesiser off 0 1 synthesiser on 1 1 reference oscillator and divider on, remainder of synthesiser circuitry off table 4. synthesiser mode control 16 bit divider charge pump pdout phase detector fch from bus (16 bit) reset comparison frequency (from reference divider) vcofin up f down f fig.3 reference divider configuration ? 8 ? 8/9 rd1 ? 4/5 rd2 ? 2/4 rd3 ? 1/2/3/4 rd4 rd5 crystal frequency 128 or 144 mhz comparison frequency 200 khz clock to demodulator
5 ZIF600 fig.5 response of data0 and data1 to a 4.8khz i/q input digital demodulator by using digital signal processing techniques it is possible to get a very robust demodulator for 4-level fsk. the demodulator produces a digital level depending on the received frequency. a digital data slicer is used to encode the data0 and data1 signals. extra functions are included to give an afc signal to the 8 bit trim dac for the crystal oscillator. the dac output will lag the incoming data, and will require some external filtering to smooth dac transitions (it is recommended to connect a 10 m f capacitor from dacout to ground). the demodulator receives "i" and "q" signals from the zif100. fig.5 shows the data0 and data1 response to a 4 level i/q input at 4.8khz from te zif100. table 5 maps the input frequency represented by the i/q demodulator inputs to the data0 and data1 outputs. the decoder will recover the symbol clock and sample the data0 and data1 signals at the appropriate time. data1 will have multiple edges during symbol transmissions. in a typical application the ZIF600 receives real time control from a decoder interface and provided the decoder with data0 and data1. fig.6 illustrates the sequence of applied signals from the decoder in a typical application. note that other system ics will require additional contol, and this may affect the sequencing given. data1 data0 frequency deviation 1 0 +4.8khz 1 1 +1.6khz 0 1 ?1.6khz 0 0 ?4.8khz table 5. frequency map for data output pins dsc2 dsc1 demodulator mode 0 0 off, hold data slicing and afc loop values 1 0 on, fast tracking for data slicingand afc loop 0 1 on, slow tracking for data slicingand afc loop 1 1 off, hold applied to data slicing and afc loop values table 6. demodulator mode control srf symbol rate 0 symbol rate filter 1600sps 1 symbol rate filter 3200sps table 7. symbol rate filter control i (4.8khz) q data0 data1 symbol transitions jitter typical sampling point
6 ZIF600 fig.6 control signal timing diagram for ZIF600 receiving data previous signal bs1 "a" -> frame info sync 2 block 0 block 10 next signal off hold slow track fast track pll settle off signal zif 600 mode vref pllc dsc1 dsc2 srf 1.25v 0v 45ms 20ms 70ms 25ms 1?6 sec. vref on xtal on synth. on demod. off fast track on srf=1600 demod. on synth.on fast afc on slow track on srf=1600 or 3200 demod. on synth.on slow afc on hold track srf=1600/3200 demod. on synth.on hold afc srf=1600 demod. off synth.on hold afc all off all off control bus the ZIF600 has its synthesiser and demodulator configured by a three wire control bus (clock, data, le). the ZIF600 must have these commands applied to it before it can be used. each command must be complete. data is clocked into the ZIF600 on the rising edg of the clock. data is latched into the internal registers when enable is high. since the enable pin gives a direct load and also resets some circuits, there will be a phase discontinuity if data is loaded after the synthesser has settled. the bus clock does not need to run between messages and to minimise interference to radio receiver circuits it is recommended that the clock is stopped whenever it is not needed. fig. 7 shows the format of the control bus. fig.7 control bus waveforms control bus timing (provisional) th ts tpw tse tpe 20ns 20ns 50ns 20ns 50ns clock data le th ts tpw tse tpe b15 b0 clock data le add
7 ZIF600 programming format (preliminary) time order first...... ...last bit no. (b) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add synthesiser fch "0" "0" system set-up "0" "0" "0" "0" "0" "0" "0" "0" "0" dmo rd5 rd4 rd3 rd2 rd1 "0" "1" table 8. programming format within each field parameters are ordered msb first and thenin descending order. data is retained by ZIF600 until vddd is removed. name length meaning fch 16 bit word synthesiser programmable divider ratio rd5 -> rd1 5 bits programming word to set crystal reference division ratio dmo 1 demodulator only operation. set to "1" to power up only the reference oscillator and divider with "pllc" pin, generating demod. clock & leaving the remainder of pll in power down. table 9. control bus bit definitions applications information by using constant current charge pumps the synthesiser loop filter is purely passive. see fig.8. it is recommended that the primary filter is placed as close to the synthesiser circuit as possible to minimise interference caused by charge pump current pulses. the high frequency clean-up filter, if needed at all, can be placed nearer the vco as required for board layout. suggested component values for d khz comparison frequency with a 5mhz/volt vco are: r1 = 15k w c1 = 220nf cp = 18nf rf = 47k w cf = 1.8nf cp r1 c1 cf to vco pdout preliminary filter rf fig.8 typical synthesiser loop filter
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